1. Field of the Invention
The present invention relates to phase-lock-loop circuits and, in particular, to a multiple phase-lock-loop circuit for recovering a clock signal from an input data signal.
2. Background of the Related Art
A signal detector for a digital communications channel, such as the read channel of a hard disk drive, is a circuit that generates a stream of recovered data and a recovered clock signal from an input data signal which is transmitted through the communications channel. Recently, as a step towards increasing the density of data transmitted through a digital communications channel, signal detectors have begun to utilize quasi-DSP (digital signal processing) techniques to produce both the stream of recovered data and the recovered clock signal.
Some DSP-based signal detector architectures utilize a phase-lock-loop (PLL) clock recovery circuit to generate the recovered clock signal. FIG. 1 shows a simplified block diagram of a conventional DSP-based PLL clock recovery circuit 10. As shown in FIG. 1, circuit 10 includes a voltage controlled oscillator (VCO) 12, a DSP 14, and a digital-to-analog converter (DAC) 16.
In operation, VCO 12 generates a recovered clock signal RCLK which has a phase and frequency that are a function of the magnitude of a phase error signal PE. DSP 14 uses the recovered clock signal RCLK to sample an input data signal V.sub.IN to produce the stream of recovered data SRD. Ambiguous samples are typically resolved by recognizing probabilistic data patterns within the stream of recovered data SRD.
To accurately recover data from the input data signal V.sub.IN, the recovered clock signal RCLK should be "locked" onto the clock signal that was originally used to transmit the data through the communications channel. As is well-known, since the frequency of the original clock signal is used to define the individual bits within the input data signal V.sub.IN, an extracted clock signal which approximates the original clock signal can be derrived from the individual bits of the sampled input data signal.
DSP 14 uses voltage level and sequence detection circuitry to generate timing data from the sampled input data signal which indicates the phase difference between the recovered clock signal RCLK and the extracted clock signal. The timing data is then utilized to generate a digital error word DEW which represents the phase difference.
DAC 16 converts the digital error word DEW to the phase error signal PE which, in turn, adjusts the VCO 12 to change the magnitude of the phase and frequency of the recovered clock signal RCLK. The net result is that the phase of the recovered clock signal RCLK is adjusted so as to reduce any phase and frequency difference between the clock signal embedded in the incoming data and the extracted clock signal.
One problem with utilizing DSP techniques in the read channel of a hard disk drive is that data is transmitted through the read channel at different frequencies as a result of the different frequencies used to fix the data on the hard disk drive. With disk drives, each track typically contains user data which has been recorded at one clock frequency and servo data which has been fixed at another clock frequency. In addition, groups of tracks, often called zones, are frequently recorded at different frequencies. Thus, the center frequency of the extracted clock signal will change each time the read head of the hard disk drive reads a different zone of data.
One technique for accommodating the changing center frequency of the extracted clock signal is to incorporate a multiplying DAC and bias the DAC with a variable input such that its bias point corresponds to the desired frequency of the extracted clock signal. With this technique, the center frequency of the recovered clock signal RCLK can be rapidly changed by simply changing the bias on the DAC.
Another problem with utilizing DSP techniques with a read channel is that the clock recovery circuit must be able to quickly lock the recovered clock signal onto each of the zone frequencies. As stated above, to accurately recover data from the input data signal V.sub.IN, the recovered clock signal should be "locked" onto the clock signal originally used to transmit the data. Thus, to avoid excessive latency time each time the frequency of the extracted clock signal changes, the circuit must quickly lock the recovered clock signal onto the current clock frequency of the data signal.
One technique for quickly locking the frequency of the recovered clock signal onto each of the zone frequencies of the data is to incorporate a processor which "learns" the bias point which corresponds to the frequency of each type of data.
In a learning process, the processor typically sends a series of digital bias words to a DAC which drives the oscillator to produce the recovered clock signal with a corresponding series of different frequencies. The processor measures each of the frequencies and generates a "look-up" table which matches each digital bias word to a specific frequency.
FIG. 2 shows a simplified block diagram which illustrates a processor 18 connected to the PLL circuit 10 of FIG. 1. As shown in FIG. 2, processor 18 receives the recovered clock signal RCLK from VCO 12 and transmits a digital bias word DBW to DAC 16.
In operation, when data from a particular track or zone is to be read, processor 18 looks up the center frequency for that zone in the look-up table, and then generates the digital bias word DBW which corresponds to that center frequency. The digital bias word DBW then drives VCO 12 to produce the recovered clock signal at a center frequency which is close to the original center frequency.
DSP 14 then samples the input data signal V.sub.IN and produces digital error word DEW. DAC 16 combines the digital error word DEW and the digital bias word DBW to modify the phase error signal PE. Since the recovered clock signal is substantially identical to the original write-clock signal, the recovered clock signal is able to quickly lock onto the data clock frequency. When, for example, the data changes from user data to servo data, processor 18 simply looks up the center frequency of the servo data and generates a new digital bias word DBW.
The principal advantage obtained from using a learning process is that processor 18 can quickly drive VCO 12 to produce the recovered clock signal with a series of very precise center frequencies. The principal disadvantage of utilizing the learning process, however, is that the circuitry required to implement the learning process consumes a significant amount of die area, power, and processing time.
In addition, if the oscillator does not have low thermal (or other) drift characteristics, then the learning process must be periodically repeated to insure that the look-up table remains accurate. Thus, there is a need for a DSP-based PLL clock recovery circuit that can quickly lock the recovered clock signal onto an extracted clock signal which has a changing center frequency without utilizing a learning process.